1. Field of the Invention
This invention relates to flash analog-to-digital converters that use a plurality of comparators in performing analog to digital conversion.
2. Description of the Related Art
Analog-to-digital conversion is used to interface a system using analog signals capable of continuous variation to an electronic system using discrete digital signals. The reverse operation of digital-to-analog conversion may also be used.
FIG. 1 illustrates an embodiment of a typical prior art parallel analog-to-digital converter (ADC) 100, also known as a flash converter. An analog input voltage signal (INPUT) 105 is input to a plurality of comparators 115. Generally, a large number of comparators are used, such as 256 comparators. A reference voltage signal (REF) 110 is also input to the plurality of comparators 115 through a voltage divider tree that includes a plurality of resistors 111 coupled between the reference signal 110 and ground 112. As shown, the positive input of each comparator 115 is the input signal 105, and the negative input of each comparator 115 is a comparator reference signal with a voltage between REF 110 and ground 112. The reference signal 110 applied to the negative input of each comparator 115 supplies a different comparator reference voltage according to the voltage divider tree.
The output of each comparator 115 is typically input to a latch 120. The output of each comparator 115 is stored in the respective latch 120 upon a rising edge of the clock signal (CLK) 125. The collective outputs of the comparators 115, stored in the latches 120, make up a thermometer code output 130. The thermometer code 130 is input to a decoder 135, sometimes referred to as an encoder. The decoder 135 decodes the thermometer code 130 into a multiple bit output 140. The output 140 is a digital value corresponding to the input analog signal 105.
A thermometer code 130 is typically a binary string of numbers, one binary value per comparator 115. Assigning the convention of most significant bit (MSB) on the left and least significant bit (LSB) on the right, i.e. MSB to LSB, the thermometer code 130 represents the binary output string of the plurality of comparators 115. The MSB is taken from the comparison between the input signal 105 and the reference signal 110. The LSB is taken from the comparison between the input signal 105 and the ground 112. In the thermometer code 130, each successive digit of the code changes from a xe2x80x9c0xe2x80x9d to a xe2x80x9c1xe2x80x9d as the value of the thermometer code increases. Assuming a simplified example with seven comparators, the thermometer code and the decoded output 140 could be any one of the following:
Note that thermometer code A signifies an input signal 105 that is below one-seventh of the reference signal 110. Thermometer code B signifies an input signal 105 that is above one-seventh of the reference signal 110 but below two-sevenths of the reference signal 110. Thermometer code H signifies an input signal 105 that is above the reference signal 110.
By convention, most ADCs 100 output the decode of thermometer code H as an error code since the output of the comparators 115 is other than an accepted value for a thermometer code 130. Any value above the reference signal 110 is unmeasurable, i.e. there is no way to know how far that the input signal is above the reference signal 110. An output that is not a proper thermometer code 130 is called a sparkle code, glitch or glitch error, or a misconversion error. For example, if the output of the comparators 115 were 0001011, then the decoder 135 would output an unknown code.
The reason for the error code output is that decoders 135 typically only look for the single transition from a xe2x80x9c0xe2x80x9d to a xe2x80x9c1xe2x80x9d in the thermometer code 130. If two or more transitions occur, the decoder 135 cannot properly decode the thermometer code 130, and hence the decoder 135 may output an incorrect or erroneous code. Incorrect thermometer codes may result from signal propagation delays in the circuit. For example, the output of the comparators 115 may be latched by the latches 120 at slightly different times, allowing for one latch 120F to latch a xe2x80x9conexe2x80x9d while latch 120G latches a xe2x80x9czeroxe2x80x9d.
As described above, a flash A to D converter has a large number of comparators, and each comparator is typically required to compare the input voltage with a reference voltage that is very close to its neighboring comparator. When a flash A/D converter is implemented in silicon, additional problems can arise. In a silicon implementation, the flash A/D converter must have good resolution and low offset, meaning that the error in neighboring comparators should not compound to create sparkle codes. Also, the large number of comparators result in a large amount of chip space, power consumption and noise. Further, since it is necessary to drive the input of all of the comparators, low impedance results, as well as high frequency noise due to the capacitance of the comparators.
Therefore, an improved flash analog to digital converter is desired which provides good resolution while also using a reduced number of comparators.
The present invention comprises a flash analog-to-digital conversion system and method with a reduced number of comparators. The present invention may provide good resolution with reduced chip space and power requirements, as well as reduced noise and capacitance problems.
The system comprises a reduced plurality of comparators each coupled to receive an analog input signal, and a decoder coupled to receive the outputs of the comparators. Each comparator also receives a respective comparator reference signal for comparison with the analog input signal. Each comparator is configured to output a digital value indicative of the comparison between the analog input signal and the respective comparator reference signal. The decoder is configured to output a digital representation (a digital output signal) of the analog input signal based on the result.
In one embodiment, the analog-to-digital converter includes a dynamic reference controller coupled to the first plurality of comparators and the decoder. The dynamic reference controller is configured to dynamically output one or more dynamic reference voltages to the first plurality of comparators, wherein the first plurality of comparators are operable to dynamically receive different comparator reference voltages for comparing with the analog input signal. The dynamic reference controller is operable to dynamically change the dynamic reference voltage signal(s) to provide a sliding range voltage window for use in the analog-to-digital conversion process. The dynamic reference controller may adjust only the upper voltage or lower voltage of the sliding range voltage window to grow or shrink the window, or may adjust both the upper and lower voltages to move the sliding range voltage window within the larger range of the A/D converter. The dynamic reference controller may use the input signal, the digital output signal, or a combination of both to dynamically change the dynamic reference voltage signal(s). The dynamic reference controller preferably maintains the sliding range voltage window such that the input signal is within the voltage window. The dynamic reference controller provides information regarding the sliding range voltage window to the decoder, and the decoder uses this information to adjust the digital output accordingly.
A method for performing analog-to-digital conversion is also contemplated. In one embodiment, the method includes receiving an analog signal and comparing the analog signal with a plurality of comparator reference signals to form a thermometer code representative of the analog signal. The method uses a reduced number of comparators. The method may also include dynamically adjusting the reference voltage window used by the comparators, based on the magnitude of the input signal, output signal, or both. The thermometer code is decoded, and a reference value that corresponds to dynamic adjustments of the plurality of reference signals is added to the decode of the thermometer code to produce a scaled digital decode of the thermometer code. The plurality of dynamic reference signals are dynamically adjusted, and the scaled digital decode corresponds to the analog signal.
In another embodiment, the analog-to-digital converter includes a subtracting node which receives an analog input signal and a feedback signal to produce a combined analog signal, a first plurality of comparators each coupled to receive the combined analog signal, a digital summer coupled to receive the outputs of the plurality of comparators, a register coupled to receive the digital signal from the digital summer and produce a digital output, and a digital-to-analog (D/A) converter coupled to receive the digital output and produce the feedback signal. The combined analog signal is the analog input signal minus the analog feedback signal. Each comparator is further coupled to receive a respective reference signal for comparison with the combined analog signal. The plurality of comparators are each further configured to output a digital value indicative of the comparison of the combined analog signal with the respective reference signal. Due to the analog feedback signal applied to the analog input signal, the combined analog signal input to the comparators has a much smaller voltage range. Thus, a lesser number of comparators may be used. The digital summer is configured to output a digital signal representative of the analog input signal. The register is configured to store the digital signal from the digital summer as a stored value and output the stored value as a digital output corresponding to the analog input signal. The D/A converter is configured to output the analog feedback signal indicative of the digital output. The digital summer is further coupled to receive the digital output and combine or add the digital output with the outputs of the plurality of comparators, thereby generating a final digital output corresponding to the analog input signal. A method for performing analog-to-digital conversion according to this alternate embodiment is also contemplated.
Thus, in the above embodiments, the analog input signal has a value within a first voltage range, and the analog-to-digital converter system and method performs analog to digital conversion on the analog input signal within the first voltage range. However, the plurality of comparators operate to compare the analog input signal with the plurality of reference signals using a second voltage range which is less, typically much less, than the first voltage range. For example, the second voltage range used by the plurality of comparators may be less than one half, one fourth, or one eighth, or even less, than the first possible voltage range of the input analog signal.